Conventionally, in a general purpose memory conforming to international standards for DRAMs, since control methods for these devices are common throughout the world, general purpose controllers for controlling such memory devices inevitably exist. Also, it is common place for a general main processor unit (MPU) to have a standardized general purpose memory controller built in.
On the other hand, since a general purpose controller can not be used with a non-general purpose memory, users must develop their own custom controller.
Conventional non general purpose memories have been developed to satisfy demands that can not be achieved using general purpose memories.
Maintaining the functions of the non-general purpose application, use of accumulated information stored inside the memory would be extremely convenient if this information could be directly accessed from a general purpose DRAM controller or an MPU having a general purpose DRAM controller.
Non general purpose memories are basically being designed making use of general purpose memories. Accordingly, it is possible to improve the design of control input signals that are extremely similar to those of a general purpose DRAM. However, it is not possible to achieve exactly the same control.
The timing of DRAM control signals generated from a DRAM controller and the timing at which memory output is latched is fixed, which means that it is extremely difficult to provide memory control that improves on control that is very similar that of general purpose DRAM.
Signals are output from a memory side to a memory controller of an MPU, and the basic concept of the present invention is to control the operation of the controller or MPU.
A specific example of a system using the conventional method will now be described.
A keyboard or a mouse is a human interface for a personal computer (hereinafter referred to as a PC). However, a digital video camera has recently become popular as a human interface. It is possible to transfer a digital image taken by the digital camera to a PC.
An dedicated memory called a field memory (referred to as FRAM below) is usually used in a digital camera (operation will be described later). A simplified block diagram of a video camera system that can transfer a digital image to a PC is shown in FIG. 1.
The operation of the video camera system of FIG. 1 will now be described.
First of all, the video camera section A will be described. An image (a) is taken in and a charged coupled device (CCD) (B) generates corresponding analog data (b). This analog data (b) is converted into digital data by an analog to digital converter (A/D) (C), and is input to the FRAM (G). Accumulated digital image data is then processed taking advantage of digital image techniques such as time axis correction and filtering, according to control signals (d) of the controller (D).
On the other hand, when considering an interface between the video camera and a PC, since the image data is extremely large, problems arise such as the fact that a buffer for temporary storage becomes large and the time taken to transfer the image data to the PC becomes excessive. Accordingly, it becomes necessary to compress the image data, and the method generally used is called JPEG compression (actually, there are various compression methods, and the present invention is not limited to JPEG compression, but JPEG compression will be used here). In JPEG compression, complicated computation is required, and the load on an MPU is substantial.
In order to carry out JPEG compression, it is therefore currently necessary to include an MPU (H) and a general purpose DRAM (M, I, J) controlled by the MPU in the conventional video camera section. Functions of the general purpose DRAM, such as a temporary buffer (M), a compression data buffer (I), and a work area (J) are separated.
The MPU (H) can not directly access the FRAM (G), and so image information (e) stored in the MPU (H) must be transferred to the temporary buffer (M) beforehand. Image information (e') in the temporary buffer (M) is subjected to compression by the MPU (H), and the compressed output data (h) are stored in a compression data buffer (I). Work area (J) is used as a work in progress work area.
Compressed data (f) stored inside the compression data buffer (I) are transferred to the PC via the interface (K). Compressed data (f) can also be expanded in the video camera and transferred to an FRAM.
Next, an FRAM widely used in television related systems will be described as an example of a memory that is not general purpose.
FIG. 3 is a circuit diagram, of a conventional FRAM. A memory cell unit Qij (i=1-m, j=1-n) is comprised of a capacitor and a transistor. As shown in FIG. 3, the sense amplifiers SAi (i=1-m) are connected to bit line pairs BLi, BLi/ connecting a plurality of memory cell units, in serial memory column units A.
The bit line pairs BLi, BLi/ (i=1-m) are connected at one end through opening and closing means Trib, Trib/ being opened and closed by an opening and closing signal WRT to write data register units Fi1 (i=1-m), and are connected at the other end through opening and closing means Tric, Tric/, being opened and closed by an opening and closing signal RTR, to read data register units Fi2 (i=1-m).
The write data register units Fi1 (i=1-m) are connected, via opening and closing means Tria, Tria/, being opened and closed by an output WYi (i=1-m) of the Y decoder means for use in a write operation B, to data transfer means (write data bus pair) WD, WD/ for connecting to input means D which receives as input an input enable signal DIE. An input terminal DI is connected to the input means D.
The read data register units Fi2 (i=1-m) are connected, via opening and closing means Trid, Trid/ being opened and closed by an output RYi (i=1-m) of the Y decoder means for use in a read operation C, to data transfer means (read data bus pair) RD, RD/ for connecting to output means G which receives as input an output enable signal DOE. An output terminal DO is connected to the output means G.
A word line WLj (j=1-n) is selected by X decoder means E receiving write X address WXA, read X address RXA and a word line drive signal PW as inputs.
Write Y address WYA and Y address drive signal WCL are input to the Y decoder means for use in a write operation B, while read Y address RYA and read Y address drive signal RCL are input to the Y decoder means for use in a read operation C.
Y address buffer P, receiving external Y address signal YAD as input and outputting write Y address WYA and read Y address RYA is controlled by a control signal SRW for determining whether an output address is a read or a write (if the Y address buffer is separate for read and write, this signal is not necessary), and read address capture signal RADE and write address capture signal WADE.
X address buffer Q receiving external X address signal XAD as input and outputting write X address WXA and read X address RXA is controlled by a control signal SRW for determining whether an output address is a read or a write (if the X address buffer is separate for read and write, this signal is not necessary), and read address capture signal RADE and write address capture signal WADE.
The memory control signal generating circuit R receiving external input signals of a read clock signal RCLK, a read enable signal RE, a write clock signal WCLK, a write enable signal WE and an address enable signal ADE outputs the previously mentioned memory control signals, namely the read address capture signal RADE, write address capture signal WADE, output enable signal DOE, input enable signal DIE, control signal SRW, write Y address drive signal WCL, read Y address drive signal RCL, opening and closing signals RTR, WTR, and word line drive signal PW.
The circuit operation of the conventional FRAM shown in FIG. 3 will now be described with respect to time using FIG. 5 and FIG. 6.
(1) Read operation (refer to FIG. 5)
At time t0, signals XAE and RYAE become H level in synchronism with read clock signal RCLK, and external address signals XAD, YAD are taken in. After that, a word line WLn is selected and memory information (Information that will be read out from here) is put on the bit line pair BLi, BLi/ (i=1-m). Operation after the above described operation is called "read transfer".
Next, at time t1 an opening and closing signal RTR is set to a high level, and the memory information on the bit line pair BLi, BLi/ (i=1-m) is transferred to a read data register unit Fi2 (i=1-m).
At time t2, the transfer that started at time t1 completes, and the word line WLn is dropped. At time t3, the read enable signal RE becomes a high level and the DRAM section returns to a reset state.
At time t4, signal YR1 rises in synchronism with the read clock signal RCLK, and information accumulated in the read data register unit F12 is transferred to the read data bus pair RD, RD/ and information DO is output by the output means.
At time t5, similarly to the operation at time t4, signal YR2 rises in synchronism with the read clock signal RCLK, information accumulated in the read data register unit F22 is transferred to the read data bus pair RD, RD/ and information DO is output by the output means.
The above operation is repeated up until time t6, and serial output is realized.
(2) write operation (refer to FIG. 6)
At time t0, signals XAE and WYAE become high level in synchronism with write clock signal WCLK, and external address signals XAD, YAD are taken in.
Next, at time t1, input enable signal DIE becomes a high level (not shown in FIG. 6), and input information DI inputted by the input means is transferred to the write data bus pair WD, WD/, and transferred to the write data register unit F11 when the signal YW1 becomes high in synchronism with the write clock signal WCLK.
At time t2, similarly to the operation at time t1, input information DI is transferred to F21 by signal YW2 becoming a high level in synchronism with write clock signal WCLK.
By repeating similar operations up to time t3, input information DI is transferred to write data register unit Fk1 in synchronism with the kth rising of the write clock signal WCLK counting from time t1.
At time t4, after a fixed time has elapsed from time t3, information that has been transferred to the write data register unit Fi1 (i=1-m) is transferred to the bit line pair BLi, BLi/ by opening and closing signal WTR. The opening and closing signal WTR goes high on the falling of write enable signal WE after time t3, or as a result of another external signal. At the same time, the information is transferred to a DRAM memory cell connected to word line WLn that is activated via that word line Wln. Operation after the above described operation is called "write transfer".
Finally, at time t5, transfer to the DRAM memory cell is completed, the word line WLn is dropped, and the memory circuit is put in a reset state.
The conventional FRAM has a problem that direct access can not be made from the general purpose DRAM controller section of the MPU (or the general purpose DRAM controller). Because of this, image information being stored within the FRAM memory cells must be stored again in a general purpose DRAM that can be controlled from a control section of the MPU. Also, the memory capacity of a temporary buffer (M) is wasted.
It is preferable for the FRAM to be controlled by the DRAM controller, but this is impossible in a conventional FRAM. Since an FRAM is basically designed as a DRAM, it is possible to utilize an interface circuit for modifying to very similar control. However, complete access is not possible using a control signal generated by the general purpose DRAM controller, because of the specific circuit system of the FRAM. For example, a general purpose DRAM is basically controlled by two signals, RAS/ and CAS/, but after an MPU has made both signals active, memory output is taken in at a determined timing. However, the FRAM has a problem in that it can not be made to provide an output for a certain period.
In a memory such as a conventional FRAM, in which a data register group (Fi1, Fi2 in FIG. 3 (i=1-m)) is connected to a DRAM memory cell and high speed access is possible, it can basically be operated using only necessary control signals among the control signals for a general purpose DRAM, since the active component is the DRAM. However, operation is different from a general purpose DRAM because of the feature that data is indirectly accessed in the memory array through a data register. Accordingly, this difference is responsible for the major drawback that the FRAM can not be controlled using a DRAM controller that is generally available on the market. For example, the fact that a write access requires the time tWD necessary for the write transfer shown in FIG. 6, and the fact that a read access requires the time tRD necessary for a read transfer shown in FIG. 5, is different from a general purpose DRAM.
Recently, highly functional MPUs have been making significant and rapid inroads into the market, and it has become commonplace for them to have a built in memory controller for general purpose use. However, an FRAM is not supported since it is not a general purpose memory. Particularly, in a digital still camera, image information stored in an FRAM must be compressed by the MPU using JPEG compression or the like. However, in the conventional art, since the FRAM can not access the DRAM controller built into the MPU, information in the FRAM must be transferred to the general purpose DRAM in order to carry out the compression processing. If the FRAM could access the DRAM controller, this problem would be solved.
The points of difference between an FRAM and a typical general purpose DRAM are that a write access involves a write transfer operation, and a read access involves a read transfer operation (and if there is self refresh, then a self refresh operation). In a typical DRAM controller of the related art, an access can not wait during a control operation, and particularly during the above mentioned time tRD (for example, in a general purpose DRAM since output data is output immediately after an address has been input, an output is strobed on the controller side after the address has been input), and a write transfer operation (or in the case of a self refresh function, a self refresh operation) is an operation internal to the FRAM, and since determination can not carried out from the controller side (that is, from outside) a normal DRAM controller (which can arbitrate access operations) can not control an FRAM.